- Internship · Intern
- 0+ years
Assist with transistor-level design and simulation of DDR I/O circuits, analyze timing, power, signal integrity, and PVT variations, contribute to design and verification of TX, RX, clocking, calibration, and power-delivery circuits, develop simulation testbenches, debug schematic and layout, document findings, and gain hands‑on experience with DDR/LPDDR PHY development.
Responsibilities
- Assist with transistor-level design and simulation of DDR I/O circuits
- Analyze timing, power, signal integrity, and PVT variations
- Contribute to the design and functional verification of TX, RX, clocking, calibration, and power-delivery circuits
- Develop simulation testbenches and automate result analysis
- Debug schematic, layout, and post-layout simulation results
Requirements
- BS or MS in Electrical Engineering or related discipline
- Nice to have: DDR
- Nice to have: LPDDR
- Nice to have: high-speed interfaces
- Nice to have: Cadence