- Austin, Texas, United States
Architect responsible for defining timing, power, and clocking methodologies for AMD's next‑generation processors and GPUs.
Responsibilities
- Drive PVT corners and frequency targets
- Drive IP physical implementation recipes from synthesis to route
- Co‑develop RTL and PD to identify bottlenecks
- Drive budgeting, measurement, analysis and tracking of power consumption
- Establish global methodologies and best‑known physical implementation recipes
Requirements
- MS/PhD in Electrical Engineering
- Nice to have: Sub‑micron process design
- Nice to have: CPU architecture
- Nice to have: GPU architecture
- Nice to have: Power‑analysis tools (Prime Power, Power‑Artist)