- Bangalore, Karnataka, India
- Principal
- 10+ years
Senior technical authority for complex custom SoC designs, defining DFT strategy and architecture, leading high-impact initiatives, and influencing cross-functional technical direction.
Responsibilities
- Define DFT strategy, architecture, methodology, and signoff criteria for complex SoCs and multiple interdependent technical areas.
- Lead high-impact DFT initiatives spanning planning, risk management, execution, manufacturing readiness, silicon quality, and test cost.
- Architect scalable solutions for scan and ATPG, compression, memory test and repair, logic BIST, test access, boundary scan, IJTAG, and mixed-signal test.
- Establish readiness and signoff frameworks, close critical risks, and provide evidence-based recommendations to engineering and program leadership.
- Solve critical DFT problems of exceptional complexity and establish reusable approaches across products and teams.
Requirements
- Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of relevant experience; or bachelor’s degree with 15+ years of relevant experience.
- Nice to have: advanced DFT methodologies
- Nice to have: hierarchical ATPG
- Nice to have: streaming scan
- Nice to have: logic BIST