Lead process integration engineering within a semiconductor manufacturing environment, managing a team of integration engineers and driving cross‑functional alignment to achieve product performance, yield, quality, and manufacturability targets.
Compensation
$138,900.00 - $182,280.00
Responsibilities
Own and drive end‑to‑end process integration across probe card manufacturing flows
Define, maintain, and continuously improve integrated process flows
Identify integration risks, process interactions, and trade‑offs impacting yield, performance, and manufacturability
Lead integration‑level yield improvement initiatives using data‑driven analysis
Drive root cause identification and resolution of complex yield excursions and defect mechanisms
The Sr. Staff Integration Engineer is responsible for defining, optimizing, and sustaining end-to-end process integration flows for probe card manufacturing in a high-volume semiconductor environment.
Compensation
$163,400.00 - $214,410.00 per year
Responsibilities
Define, own, and continuously improve end-to-end process integration flows for probe card manufacturing
Ensure alignment of unit process performance to product-level electrical, mechanical, and reliability targets
Identify and manage integration risks, interactions, and trade-offs across modules
Lead integration-level yield improvement initiatives using data-driven analysis and structured problem solving
Investigate complex yield excursions, defect mechanisms, and cross-process interactions
Define and own the manufacturing quality strategy for infrastructure hardware programs, including compute, GPU, storage, and networking platforms, across NPI and mass production phases
Establish and track key manufacturing quality metrics including yield, first-pass rate, defect density, and field return rates, driving accountability and continuous improvement across internal teams and contract manufacturing partners
CMP Process Engineer
Samsung Austin Semiconductor, LLC · Posted Nov 4, 2026
A CMP (Chemical Mechanical Polishing) Process Engineer is responsible for the critical semiconductor manufacturing step of planarizing the wafer surface.
Compensation
The current base salary range for this role is between $106,000 - $145,000. Individual base pay rates will depend on factors including duties, work location, education, skills, qualifications and experience. Total compensation for this position will include a competitive benefits package and may include participation in company incentive compensation programs, which are based on factors to include organizational and individual performance.
Responsibilities
Removal Rate (RR) Control
Condition Optimization
Recipe Management
Defect & uniformity Management
Consumable Life Cycle Management
Requirements
BS or MS in Chemical, Mechanical, Electrical, or Industrial Engineering, Physics, Chemistry, Material Science, or Computer Science
Nice to have: Familiar with Metrology Tools
Nice to have: Experience with Ellipsometry, SEM, and AFM
Lead and manage quality planning across supplier, manufacturing, and product domains for Mahindra’s international operations in Algeria, ensuring compliance with APQP, PPAP, FMEA, and continuous improvement initiatives.
Locations (2)
Mumbai, Maharashtra, India
Algeria
Responsibilities
Drive supplier quality assurance, supplier development and supplier performance improvement.
Ensure robust manufacturing quality systems across aggregate and vehicle assembly operations.
Lead product quality assurance activities, including final tractor quality, customer complaints and warranty reduction.
Drive APQP, PPAP, FMEA, Control Plans, Process Audits and Product Audits.
Lead root cause analysis and corrective actions for supplier, manufacturing and field quality issues.
Continuously evaluate and enhance test coverage, methodologies, and infrastructure to improve hardware reliability and performance at scale against defined targets
Lead root cause analysis and corrective action programs for systemic hardware failures, managing failure analysis workflows and driving closure of critical issues against defined yield and reliability targets
Partner with cross-functional engineering teams to drive power optimizations and performance tuning for compute and GPU systems during the manufacturing validation phase
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