FinFET process nodes jobs

Principal ASIC Synthesis and Timing Engineer

K2 Space · Posted Nov 12, 2026

Remote, United States
Remote
Full-time · Principal
$190K–$280K per year
10+ years

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Lead the implementation of complex SoCs for next-generation satellite and space systems, owning constraints development and validation from RTL handoff to synthesis.

Compensation

Base salary range for this role is $190,000 – $280,000 + equity in the company

Responsibilities

Own the complete RTL-to-Synthesis flow
Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA)
Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration
Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools
Own Lint, CDC and UPF checks and drive collaboration to close out issues

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
Nice to have: radiation-hardened ASICs
Nice to have: physical design service vendor management
Nice to have: TSMC tapeouts
Nice to have: Gate-All-Around technologies

Skills

ASIC design RTL-to-GDSII flows timing closure

Principal ASIC Physical Design Engineer

Principal ASIC Physical Design Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

Principal ASIC Synthesis and Timing Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits