The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks
Lead verification of complex FPGAs within Lattice’s Silicon Engineering team, integrating IP-level design and verification environments, crafting UVM testbenches, and ensuring tape‑out readiness.
Responsibilities
Verify complex FPGAs and SOC architectures
Integrate IP-level design and verification environments
Craft UVM testbenches and reusable verification infrastructure
Implement coverage-driven and directed test cases
Deploy new tools and methodologies to improve quality of tape‑out readiness
Serve as the primary technical resource for the verification team, leading end-to-end verification of IPs and their integration using best-in-class methodologies.
Responsibilities
Serve as the primary technical resource for the verification team, providing expert guidance.
Act as the central liaison to other verification and methodology teams at Infineon to coordinate strategies and resolve issues centrally
Lead and execute end-to-end verification of IPs and their integration using best-in-class methodologies (e.g., formal verification, AI-assisted testing)
Lead and review the third-party’s verification methodology and execution, from planning through implementation to final sign-off
Drive vendor accountability to close gaps and meet milestone targets
Requirements
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field
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