- Pune, Maharashtra, India
- Senior
- 14+ years
Senior Staff design engineer responsible for RTL development of machine learning engines on low‑power FPGA platforms.
Responsibilities
- Develop and enhance RTL for machine learning engine
- Implement ML operators efficiently on low‑power FPGA
- Optimize data path for high throughput and low latency
- Collaborate with algorithm and architecture teams to translate ML models into efficient hardware micro‑architectures
- Design RTL for machine learning compute engines targeting low‑power FPGA platforms
Requirements
- BE/MTech/PhD in Electronics, Electrical or Computer Engineering
- Nice to have: Experience with C
- Nice to have: Experience with SystemC