Senior Design Engineer – Modeling position develops, validates, and delivers IP behavioral models and related hardware collateral used by internal engineering teams and software-facing customers.
Responsibilities
Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
Translate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.
Perform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.
Lead or support the generation, audit, validation, and release of timing, power, signal-integrity, configuration, and metadata deliverables used for hardware and software integration.
Investigate and resolve model behavior, hardware-to-software integration, and customer-facing issues across the IP development lifecycle.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field
We are seeking a Principal FPGA Micro-Architect with deep expertise in programmable logic fabric design and a track record of delivering next-generation FPGA devices from concept to silicon.
Compensation
Base Pay Range 250,000.00. In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Drive fabric PPAU (power, performance, area, and utilization) optimization; evaluate implementation and routing feasibility and drive design trade-offs for modularity and scalability across device generations
Develop SystemC/C++ architectural models to drive performance analysis and evaluate fabric design trade-offs ahead of RTL/schematic availability
Lead advanced low-power fabric design including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching
Drive software primitive definition and implementation strategy, ensuring fabric elements are optimally mapped to CAD tools and customer design flows for maximum usability
Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, focusing on ASIC development and verification.
Responsibilities
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing
Oversee definition, design, verification, and/or documentation for ASIC development
Determine architecture design, logic design, and/or system simulation
Define module interfaces/formats for simulation
Lead the development of multidimensional designs involving the layout of complex integrated circuits
Requirements
Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
Bachelor’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
The role focuses on SoC performance analysis, collaborating across hardware and software teams to define and engineer next-generation SoC product architectures.
Compensation
$129,500.00 - $194,300.00
Responsibilities
Engineer market-leading SoC products with best-in-class performance
Lead and conduct performance and systems studies
Conduct or contribute to analysis to define our SOC architecture plans simultaneously taking into account performance, power and thermal
Collaborate with HW and SW teams to define best-in-class multimedia, modem, compute and memory technologies
Define complex use cases including new workloads (Gaming, AI) and infer systems requirements
Lead verification of AMD’s graphics processor IP, ensuring bug-free designs through test planning, execution, and collaboration with architects, hardware, firmware, and software teams.
Responsibilities
Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified
Build test plan documentation accounting for interactions with other features, hardware, firmware, and software driver use cases
Estimate time required to write new feature tests and required changes to test environment
Build directed and random verification tests
Debug test failures to determine root cause and resolve design defects
Requirements
Bachelor's or Master's degree in Computer Engineering or Electrical Engineering
Nice to have: Leadership or mentorship experience
Nice to have: Exposure to video codec system or other multimedia solutions
Senior Hardware Architect focused on Reliability, Availability, and Serviceability (RAS) for Tegra System-on-Chips.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 184,000 USD – 287,500 USD for Level 4; and 224,000 USD – 356,500 USD for Level 5.
Responsibilities
Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.
Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
Work closely with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
Understand the broader SoC architecture and identify how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
Requirements
MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
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