- Munich, Bavaria, Germany
- On-site
- Senior
Senior Circuit Designer within our Digital Design Engineering group, responsible for developing innovative ASICs and leading SRAM compiler IP requirements.
Responsibilities
- Drive the development of SRAM, register files, and latch arrays to enable high-performance, low-power design.
- Lead the SRAM compiler IP requirements for foundry, vendors, and internal IP teams.
- Understand the complete design flow spectrum, including DFT and testing aspects of compiler IPs, and integrate them into our SOCs.
- Collaborate with logic/architecture teams to capture specifications of SRAM, register files, and latch arrays, driving their implementation.
Requirements
- Bachelor’s in Electrical Engineering (BSEE)
- Nice to have: Masters/PhD in Electrical Engineering
- Nice to have: tape-out of high-performance, low-power circuit design
- Nice to have: ML-based programming algorithms
- Nice to have: automation solutions for rapid and dynamic design