Leads the global Hardware Engineering organization for GlobalFoundries’ MIPS Custom Silicon business, responsible for delivery of custom MCUs, MPUs and Sensor SoCs.
Responsibilities
Lead and scale the global hardware engineering organization covering RTL, DV, DFT, and Physical Design for custom silicon programs.
Own hardware execution strategy for MIPS‑based MCUs and radar SoCs, ensuring predictable delivery across multiple concurrent customer engagements.
Establish and enforce engineering standards, design methodologies, quality metrics, and best practices across all hardware disciplines.
Partner with Product Management and Systems Architecture to translate customer and platform requirements into executable hardware roadmaps.
Drive cross‑functional alignment with Software, Program Management, Manufacturing, Test, and Quality teams to ensure end‑to‑end silicon readiness.
Lead the development, integration, and productization of high-performance interface solutions for FPGA products.
Responsibilities
Lead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related interface subsystems.
Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
Drive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
Work with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.
Drive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
The role involves working on floor-planning, timing constraints, physical synthesis, and block level place and route from Netlist through GDS flow.
Responsibilities
Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
Collaborate on executing the block level place and route assignments from Netlist through GDS flow.
Interact with design team with purpose to solve problems and propose physical design engineering ideas.
Coordinate all timing budgeting required for physical design task with respective teams.
Close STA timing across all corners and modes for blocks and should be able to generate ECO independently.
Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Collaborate on executing the block level place and route assignments from Netlist through GDS flow
Interact with design team with purpose to solve problems and propose physical design engineering ideas
Coordinate all timing budgeting required for physical design task with respective teams
Close STA timing across all corners and modes for blocks and should be able to generate ECO independently
Design / DFT Director (NVE Engineering)NewMicron Technology · Avezzano, Italy