- Hsinchu, Taiwan, Taiwan
- 6–7 years
Packaging Engineer responsible for manufacturing readiness, yield, quality, and process improvement of advanced semiconductor packages.
Responsibilities
- Own manufacturing readiness for new product bring-up of InFO, EFB/CoWoS-L, CoWoS, WLFO, FCBGA, LGA, and chiplet packages at the manufacturing site.
- Own packaging yield, quality, cost, and operational productivity improvements, as well as sustaining activities.
- Drive assembly process baseline standardization and continuous improvement.
- Own packaging interaction activities across assembly, bump, 3D IC, HBM, wafer fab, wafer sort, functional test, and mark/pack.
- Drive the assembly manufacturer to enhance process, equipment, and material capability for future-generation technologies and products.
Requirements
- Bachelor's in Mechanical, Materials, or Chemical Engineering
- MS in Mechanical, Materials, or Chemical Engineering
- Nice to have: InFO
- Nice to have: chiplet packaging
- Nice to have: 2.5D/3D TSV/packaging