- Full-time · Manager
- 5–10 years
Design and develop high-speed IO circuits for next-generation memory interface PHY IPs including DDR, HBM, and UCIe in advanced CMOS, FinFET, and GAA process nodes.
Responsibilities
- Design and develop high-speed IO circuits for next-generation memory interface PHY IPs
- Execute circuit design tasks from architecture through layout, simulation, and verification with a focus on performance, power, and area optimization
- Analyze and solve complex analog design challenges in advanced technology nodes
- Collaborate with global cross-functional teams to deliver integrated PHY solutions
- Apply ESD and reliability principles to ensure robust circuit design
Requirements
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field
- Nice to have: knowledge of JEDEC memory interface standards (DDR, HBM, LPDDR)
- Nice to have: familiarity with signal integrity and power integrity concepts