- San Jose, California, United States
- Full-time · Senior
- $144K–$230K per year
- 12–10 years
STA & Timing Closure Engineer to lead static timing analysis and signoff execution for high-complexity, multi-GHz System-on-Chip (SoC) architectures on advanced FinFET and GAA nodes (5nm, 3nm, 2nm).
Compensation
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
Responsibilities
- Architect, configure, and maintain rigorous STA environments across hundreds of process, voltage, temperature (PVT), and operational modes
- Develop, audit, constraints for complex clock structures
- Collaborate closely with physical design teams to analyze timing bottlenecks; generate precise ECOs—both automated and functional/manual
- Validate timing margins against foundry standard cell, macro, and interface IP characterization data
- Run strict signoff audits to guarantee zero critical timing violations prior to tapeout
Requirements
- BS Degree in Electrical Engineering
- MS in Electrical Engineering