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Skill:Memory system architecture

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1–2 jobs· newest first

Agentic AI EngineerNew
Booz Allen Hamilton · Annapolis Junction, US
$78K–$176KFull-time
ASIC Design Verification Engineer, Machine Learning
Google · Sunnyvale, US
$138K–$197KOn-site · Full-time · Mid

+10K new in the last hour

Agentic AI Engineer

Booz Allen Hamilton · Posted Nov 9, 2026

Annapolis Junction, Maryland, United States
Full-time
$78K–$176K per year
5+ years

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Design, build, and deploy autonomous AI agents for U.S. Cyber Command operations, enhancing mission effectiveness and operational capacity.

Compensation

The projected compensation range for this position is $77,600.00 to $176,000.00 (annualized USD).

Responsibilities

Design and develop AI agents capable of autonomous multi-step workflows
Integrate tools, APIs, and external services into AI-driven systems
Build and maintain memory systems for agent state and retrieval
Implement inference request flows with latency and batching management
Write integration tests for multi-service systems

Requirements

Bachelor's degree in Computer Science, Engineering, or Data Science
Nice to have: Multi-agent workflow architecture
Nice to have: State machine design
Nice to have: Planner and decision-graph logic
Nice to have: Evaluation and observability

Skills

Python AI agent development LLM workflow design API integration Memory system architecture Inference request flow implementation Integration testing Containerization CI/CD Distributed systems TS/SCI clearance AWS Bedrock Google Gemini Microsoft Foundry Redis PostgreSQL Docker Kubernetes IaC

Benefits

Health, life, disability, financial, and retirement benefits
Paid leave
Professional development
Tuition assistance
Work-life programs

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ASIC Design Verification Engineer, Machine Learning

Google · Posted Nov 4, 2026

Sunnyvale, California, United States
On-site
Full-time · Mid
$138K–$197K per year
4+ years

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ASIC Design Verification Engineer focused on TPU technology and AI/ML hardware acceleration for data center applications.

Compensation

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry-leading formal tools.
Identify and write all types of coverage measures for stimulus and corner cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
Nice to have: computer architecture
Nice to have: silicon-based ICs and chips

Skills

design verification

memory system architecture

Benefits

bonus
equity
benefits

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