- Penang, Malaysia
- Senior
- 6+ years
Design and develop FPGA software tools and IP at Lattice in Penang.
Responsibilities
- Design and implement DSP foundation IP blocks
- Develop RTL for DSP hard macros and programmable DSP slices
- Perform functional simulation and timing analysis
- Engage with software and tools teams to model DSP IP in simulation libraries and synthesis flows
Requirements
- Bachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline
Skills
RTL design using Verilog, VHDL, or SystemVerilogDSP theory and algorithms: filtering, FFT, fixed-point arithmetic, sample-rate conversionFunctional verification methodologies (SystemVerilog Assertions, formal verification)Synthesis and static timing analysis tools (Synopsys Design Compiler, PrimeTime, Radiant, Quartus)