- Bangalore, Karnataka, India
- 8+ years
Lead Full-Chip Floorplan Engineer responsible for physical implementation planning of complex SoCs and ASICs.
Responsibilities
- Develop and own top-level SoC floorplan architecture
- Define chip aspect ratio, die size, partitioning strategy, and hierarchy planning
- Perform macro placement and optimization for timing, congestion, power, and thermal considerations
- Drive floorplan refinement through design milestones
- Define floorplan topology for large-scale SoCs
Requirements
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering