Debug and Trace Architect
RosaicLabs · Posted Oct 21, 2026
- Santa Clara, California, United States
- On-site
- Full-time · Senior
- 12+ years
- Visa sponsorship
Define how engineers and software teams observe and diagnose multi-die computing systems, owning run-control, trace, performance counters, and post-mortem capture from architecture definition through silicon bring-up.
Responsibilities
- Own the SoC debug and trace specification, including run-control access, a common trace record format, and observability requirements for bring-up, performance diagnosis, and failure analysis.
- Define secure JTAG and run-control behavior for compute engines, cores, management controllers, and other relevant subsystems, including halt and step capabilities.
- Specify instruction, compute-engine, microcontroller, fabric-transaction, die-to-die, and network-gateway trace sources.
- Architect trace funnels, cross-die triggers, on-chip buffers, and a synchronized package-wide time base aligned with RAS error records.
- Define trace capture and export paths, including optional spill to memory and readout over PCIe; set bandwidth limits and measure the effect of tracing on workloads.
Requirements
- Bachelor’s degree in Electrical Engineering
- Bachelor’s degree in Computer Engineering
- Bachelor’s degree in Computer Science
- Nice to have: Trace synchronization across multiple dies
- Nice to have: Timestamp alignment