Director, SoC Design Verification and Virtual Platform Quality
Renesas Electronics · Posted Nov 12, 2026
- Hyderabad, Telangana, India
- 15+ years
Lead and develop a global Design Verification organization, define and execute a reuse-first verification strategy spanning SystemC models, RTL, IP, subsystems, SoCs, and Virtual Platforms.
Responsibilities
- Define and drive the verification strategy for SystemC models, RTL designs, reusable IP, subsystems, SoCs, and Virtual Platforms.
- Lead and develop a global Design Verification organization, including verification leads, engineers, external partners, and project-specific teams.
- Establish a common verification architecture that supports reuse of test intent, stimulus, sequences, checkers, scoreboards, assertions, coverage models, and regression infrastructure across SystemC and RTL.
- Develop scalable SystemVerilog/UVM environments, including protocol adapters and TLM bridges that connect pin-level UVM interfaces to SystemC/TLM models.
- Establish functional-equivalence and timing-correlation methodologies between SystemC LT/AT models and RTL implementations.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Nice to have: SystemC/TLM-2.0 models
- Nice to have: TLM-to-signal adapters
- Nice to have: UVM/SystemC bridges
- Nice to have: DPI interfaces