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System Verilog assertion jobs

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1–2 jobs· newest first

Lead Engineer Design VerificationNew
Quest Global · Windsor, US+1 more
$172K–$172KSenior
Japan DVT FAE
Siemens · Tokyo, Japan+1 more
¥800–¥1KHybrid · Full-time

+10K new in the last hour

Lead Engineer Design Verification

Quest Global · Posted Nov 13, 2026

Windsor, Connecticut, United States +1 more
Senior
$172K–$172K per year
2+ years

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Lead Engineer Design Verification

Locations (2)

Windsor, Connecticut, United States
United States

Compensation

Salary $172,210

Responsibilities

Contribute towards bug free first-time pass silicon (Chip), understanding architecture and design of IP to make sure IP use cases are clear and IP is verified correctly with no bugs.
Plan and develop test-benches using standard methodology using different Hardware Description language (HDL).
Run simulation using industry leading tools like Synopsys VCS and Cadence Incisive.
Develop testcases in HDL for exercising scenarios.
Identify and close various functional and code coverage scenarios to achieve 100% code and functional coverage goal.

Requirements

Master’s degree in Electrical Engineering or related field

Skills

Verilog System Verilog UVM Functional coverage Code coverage Constrained Random verification System Verilog assertion C/C++Python AMBA AXI Verilog simulators Verdi Debugging Synopsys VCS Cadence Incisive

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Japan DVT FAE

Siemens · Posted Nov 10, 2026

Tokyo, Tokyo, Japan +1 more
Hybrid
Full-time
¥800–¥1K per year

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Sales Engineer providing technical solutions and support for Siemens EDA products in Japan.

Locations (2)

Tokyo, Tokyo, Japan
品川, Japan

Compensation

基本給年額：800〜1,200万円（月額給与は年俸の12分の1）

Responsibilities

提案顧客へのソリューション提案
営業同行しての顧客折衝
営業、顧客企業、海外の開発部門との調整
製品導入時のテクニカルサポート
製品資料の作成

Requirements

大学卒業以上

Skills

Verilog VHDL System Verilog IP Verification IP (UVM)

formal verification

equivalence verification

CDC verification

System Verilog Assertion

project management

Benefits

通勤手当：特急料金を除き全額支給
総合福祉団体定期保険
団体長期障害所得補償保険
福利厚生倶楽部（リロクラブ）
慶弔金

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