Providing technical leadership for automated verification across next-generation autonomy platforms, focusing on test architecture, MLOps quality systems, and CI/CD pipelines.
Responsibilities
Own the technical strategy, architecture, and roadmap for automated testing, verification, and MLOps quality across the Hivemind ecosystem.
Design and maintain scalable test frameworks for autonomy software, backend services, APIs, operator-facing applications, and distributed hardware environments.
Lead functional, integration, regression, system, performance, reliability, and end-to-end testing across simulation, edge-compute, software-in-the-loop, and hardware-in-the-loop environments.
Build automated ML validation pipelines covering data quality, training reproducibility, model accuracy, robustness, regression, latency, resource utilization, and system integration.
Establish CI/CD and continuous training workflows that provide versioning and traceability for datasets, models, configurations, evaluation results, and deployment artifacts.
Lead the Infrastructure & CI team to evolve the infrastructure that takes Zivid’s software from commit to a tested, shippable product on real hardware.
Compensation
Competitive compensation, including sign-on stock options, a competitive pension scheme and premium health insurance
Responsibilities
Lead a small team of experienced software engineers
Build and run CI, build or test infrastructure used by many teams
Make hosting decisions across cloud, on-prem and co-located infrastructure
Develop metrics-driven gates, signals and dashboards
Lead Zephyr RTOS architecture and platform enablement for MIPS RISC-V based MCU and embedded compute products.
Responsibilities
Own the Zephyr enablement architecture and technical roadmap across MIPS RISC-V processors, SoCs, FPGA platforms, and virtual development platforms.
Lead porting and platform bring-up covering boot flow, exception and interrupt handling, timers, SMP where applicable, memory architecture, devicetree, Kconfig, and build integration.
Define scalable BSP, SoC, board, and driver architecture aligned with Zephyr conventions and upstream-quality expectations.
Design and review device drivers, middleware integration, samples, tests, and production-quality SDK deliverables.
Lead complex debugging across kernel, toolchain, architecture, hardware, and driver boundaries using emulation, FPGA, and silicon.
Lead Zephyr RTOS architecture and platform enablement for MIPS RISC-V based MCU and embedded compute products.
Responsibilities
Own the Zephyr enablement architecture and technical roadmap across MIPS RISC-V processors, SoCs, FPGA platforms, and virtual development platforms.
Lead porting and platform bring-up covering boot flow, exception and interrupt handling, timers, SMP where applicable, memory architecture, devicetree, Kconfig, and build integration.
Define scalable BSP, SoC, board, and driver architecture aligned with Zephyr conventions and upstream-quality expectations.
Design and review device drivers, middleware integration, samples, tests, and production-quality SDK deliverables.
Lead complex debugging across kernel, toolchain, architecture, hardware, and driver boundaries using emulation, FPGA, and silicon.
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