- Pune, Maharashtra, India
- Senior
- 6+ years
Lead verification of complex FPGAs within Lattice’s Silicon Engineering team, integrating IP-level design and verification environments, crafting UVM testbenches, and ensuring tape‑out readiness.
Responsibilities
- Verify complex FPGAs and SOC architectures
- Integrate IP-level design and verification environments
- Craft UVM testbenches and reusable verification infrastructure
- Implement coverage-driven and directed test cases
- Deploy new tools and methodologies to improve quality of tape‑out readiness
Requirements
- BS/MS Electrical Engineering
- Computer Science
- Computer Systems Engineering
- or equivalent degree