- San Jose, California, United States
- Principal
- $185K–$240K per year
- 8+ years
Lead the functional verification of complex ASIC designs for AI fabric switches, managing the full verification lifecycle and collaborating with software and system validation teams.
Compensation
The base salary range is USD 185,000.00 – USD 240,000.00.
Responsibilities
- Plan and write verification tests using System Verilog/UVM/C/C++
- Debug and resolve RTL failures
- Develop coverage models and close coverage gaps
- Execute tests on emulation platforms
- Collaborate with RTL designers
Requirements
- Bachelor’s in Electrical Engineering
- Master’s in Electrical Engineering