- San Jose, California, United States
- On-site
- Contract · Senior
- 7+ years
A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.
Responsibilities
- Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
- Option to also do block level RTL design or block or top-level IP integration.
- Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
- Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
- Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Requirements
- Bachelor’s Degree in Electrical or Computer Engineering
- Master’s Degree in Electrical or Computer Engineering
- Nice to have: TCM (Timing Constraint Manager)
- Nice to have: CCD (Conformal Constraint Designer)
- Nice to have: Spyglass CDC