The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks
A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.
Responsibilities
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Requirements
Bachelor’s Degree in Electrical or Computer Engineering
Master’s Degree in Electrical or Computer Engineering
The Integration Design Engineer will be part of the Silicon Integration Team, responsible for integrating different IPs to build the chip using both custom and digital design flows.
Responsibilities
Integrate different IPs to build the fullchip.
Deliver all corresponding models, views, and collaterals to functional teams.
Complete all required checks and simulations for sign-off.
Collaborate with Architecture, SW, IP Design, and Physical Design Teams to generate fullchip logical floorplan.
Generate fullchip behavioral model by integrating various IP models.
An integration design engineering role focused on Custom and Digital Design Implementation, specifically using Verilog and System Verilog for programmable logic solutions.
Responsibilities
Custom Design Flow implementation
Semiconductor principles and transistor-level analysis
Characterization, performance, and power simulations
RTL coding and verification
Lint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA
Requirements
BS or MS in Electronics Engineering
BS or MS in Computer Engineering
BS or MS in Electrical Engineering
Nice to have: FPGA/CPLD design and integration
Nice to have: IP and Fullchip functional verification
The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII.
Compensation
The base salary range is $140,000 - $156,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.
Responsibilities
floor-planning
auto place and route
static timing analysis
eco implementation
signal integrity analysis
Requirements
BS/MS in EE/computer science or equivalent experience
Lead functional team of Program Control Analysts, overseeing day‑to‑day guidance, quality oversight, and workload coordination for the LIDS program.
Compensation
Total compensation for this role is market competitive. The anticipated salary range for this position based out of Syracuse, NY is estimated at $77,000 to $116,000 annually.
Responsibilities
Provide day‑to‑day guidance to the PCA team
Serve as onboarding resource for new hires
Monitor and balance team workloads
Develop and maintain project schedules, WBS structures, and cost accounts
Maintain and report program status metrics
Requirements
Bachelor’s degree in a related field (business administration, mathematics, or engineering)
Nice to have: Leading or mentoring program control or financial analysts
Nice to have: Experience on IDIQ or multi–task‑order defense programs
Nice to have: Familiarity with EVM cost tools (e.g., Cobra)
Nice to have: Experience with workforce/programmatic tools (e.g., Tempus)
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