- Sunnyvale, California, United States
- On-site
- $192K–$278K per year
- 10+ years
Compensation
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Responsibilities
- Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
- Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
- Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures.
- Manage different PNR tools - Synopsys Fusion Compiler, Cadence Innovus/Genus, PrimeTime, StarRC, Calibre, Apache Redhawk.
- Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture