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1–3 jobs· newest first

Analog Design Engineer
Teradyne · Agoura Hills, US
$104K–$167KOn-site · Full-time · Associate
Senior Principal Analog Design Engineer
onsemi · Allen, US
Senior
Senior Analog Design Engineer – Power & Clock IP
onsemi · Allen, US
Senior

+10K new in the last hour

Analog Design Engineer

Teradyne · Posted Nov 4, 2026

Agoura Hills, California, United States
On-site
Full-time · Associate
$104K–$167K per year
2+ years

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Contribute to the development of high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE).

Compensation

The base salary range for this role is $104,100 to $166,600. This range is a good-faith estimate, and the actual base salary will correspond with the candidate’s experience, skills, and location.

Responsibilities

Design, simulate, and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
Perform circuit-level verification and simulation across process, voltage, and temperature (PVT) corners using Cadence EDA tools.
Support schematic, layout, physical verification, and ASIC integration activities in collaboration with other members of the design team.
Participate in design reviews and contribute to circuit analysis, debugging, and technical problem-solving.
Support silicon characterization, laboratory measurements, debug, validation, and production test activities.

Requirements

Master’s degree in Electrical Engineering
Computer Engineering
related discipline
Nice to have: ASIC tape-out
Nice to have: silicon bring-up

Skills

analog or mixed-signal IC design CMOS circuit design simulation characterization Python SKILL Ocean PLLs DLLs ADCs DACs VCOs amplifiers clocking circuits high-speed I/Os CML circuits CMOS device fundamentals semiconductor processes PDKs PVT effects Cadence EDA

Benefits

medical
dental
vision
Flexible Spending Accounts
retirement savings plans

See full job description

Senior Principal Analog Design Engineer

onsemi · Posted Nov 3, 2026

Allen, Texas, United States
Senior
10+ years

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Lead the design, simulation, verification, and delivery of power management and clocking analog IP blocks for Treo-based SoC platforms.

Responsibilities

Design, simulate, and verify power management IP including LDOs, DC/DC converters, and charge pumps.
Design and implement clocking circuits such as PLLs, DLLs, oscillators, and clock distribution networks.
Support IP architecture definition by contributing analysis, trade‑off studies, and design proposals.
Execute schematic design, layout guidance, post‑layout extraction, and corner/Monte Carlo analysis to meet specifications.
Deliver validated analog blocks into mixed‑signal and digital‑on‑top subsystems for SoC integration.

Requirements

Nice to have: Verilog‑A/AMS/SV RNM modeling
Nice to have: automotive reliability
Nice to have: industrial reliability
Nice to have: functional‑safety requirements
Nice to have: AI/ML‑assisted design

Skills

analog IC design power management circuits clocking circuits SPICE/AMS simulation

Senior Analog Design Engineer – Power & Clock IP

onsemi · Posted Nov 3, 2026

Allen, Texas, United States
Senior
5+ years

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Develop power management and clocking IP for Treo-based SoCs

Responsibilities

Design, simulate, and verify analog IP including LDOs, DC/DC converters, charge pumps, PLLs, DLLs, and oscillators.
Own analog blocks from specification through silicon validation.
Perform schematic design, layout review, post-layout verification, and corner analysis.
Collaborate with digital, validation, and technology teams during integration and bring-up.
Support lab characterization and post-silicon debugging.

Requirements

Nice to have: Verilog-A/AMS modeling
Nice to have: automotive applications
Nice to have: industrial applications
Nice to have: AI-assisted design

Skills

analog IC design power management circuits clocking circuits SPICE/AMS simulation mixed-signal verification schematic design

variability analysis

mixed‑signal co‑simulation

jitter analysis

reliability analysis

schematic capture

layout guidance

post‑layout extraction

corner analysis

Monte Carlo analysis

SPICE/AMS simulation tools

automation tools

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post-layout verification

corner analysis

schematic capture

simulation tools

See full job description