As a Senior Manager in Silicon Design Validation, You lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products, providing strategic oversight and technical direction across the full post-silicon lifecycle.
Responsibilities
Lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products
Foster a learning environment where engineers gain hands-on experience with FPGA architectures and foundational IP blocks
Oversee the validation and characterization of analog, digital, and mixed-signal IPs
Guide the development of validation plans, including bench hardware and software requirements
Supervise the creation of custom RTL test logic to support targeted validation and characterization efforts
Design and simulation of advanced analog and mixed‑signal integrated circuits for high‑speed SerDes solutions.
Locations (2)
Cork, Munster, Ireland
Dublin, Leinster, Ireland
Responsibilities
Learn how system requirements are translated into analog and mixed‑signal circuit designs.
Support the design, simulation and optimization of transistor‑level circuits.
Work with analog building blocks such as amplifiers, bias circuits, voltage/current references, data converters, clocking circuits and high‑speed interfaces.
Run simulations across different operating conditions and analyse key performance metrics such as gain, bandwidth, noise, power, jitter and stability.
Gain exposure to custom IC layout, including matching, placement, routing and parasitic effects.
Lead the development of key circuit blocks from specification through proven silicon for advanced clock and timing products.
Compensation
At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
Responsibilities
Develop circuit specifications for high-performance timing products
Design analog and custom digital CMOS circuits for high-performance timing products
Incorporate circuit blocks into the complete chip design
Collaborate with distributed cross-functional teams, including layout, digital, system design, and validation
Early-career RF hardware systems engineer role focused on 5G radio products, RF characterization, board bring-up, and debugging.
Compensation
The base salary range for the primary location of this role is between $120,000 and $145,000 plus stock options and benefits.
Responsibilities
Get hands-on in the lab. Bring up new boards, run RF characterization and validation, and debug issues at the board and subsystem level.
Contribute to the radio design. Support schematic and PCB development for RF subsystems, including transceiver chains, impedance-controlled layout, and power distribution.
Verify against the spec. Help define test plans, run measurements, and report results against system requirements for our 5G radio products.
Work across teams. Partner with hardware, firmware, software, and Test teams to turn design decisions into clear requirements and resolve integration issues.
Help get it to production. Support design reviews and qualification so our products are ready to manufacture at volume.
Senior Analog Design Engineer responsible for architecture, design, implementation, and validation of high-speed analog and mixed-signal integrated circuits for silicon photonics solutions.
Compensation
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
Responsibilities
Architect, design, and validate high-speed, low-voltage, low-power analog and mixed-signal integrated circuits
Lead block-level design and collaborate with multidisciplinary teams
Plan and execute design activities while balancing performance, schedule, and quality objectives
Guide post-silicon test and characterization plans
Create and maintain comprehensive design documentation
Requirements
M.S. degree in Electrical Engineering or related field
Lead the design, development, and production of analog IP for the Treo BCD65 platform, including architecture definition, block development, verification, and mentoring of junior engineers.
Responsibilities
Define architectures for power, clock, monitoring and reset IP
Translate product-line requirements into IP specifications and roadmaps
Drive architecture trade-offs across performance, power, area, robustness, testability and integration complexity
Champion reusable IP architectures and interfaces
Communicate architecture proposals, roadmap priorities and technical decisions
Requirements
Bachelor's in electrical or electronic engineering
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