Lead verification of CPU-subsystem power‑management functionality across complex SoC and subsystem environments.
Compensation
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Responsibilities
Lead verification planning and execution for CPU‑subsystem power‑management features from unit and block level through subsystem integration and signoff.
Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power‑state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm‑reset flows, and multi‑domain interactions.
Own high‑value stress, corner‑case, and long‑run scenarios that expose failures in power‑state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wakeup behavior, and activity‑monitor correctness.
Partner closely with architecture, RTL, DV, and infrastructure teams to review specifications, reduce ambiguity early, and improve debugability and verification completeness before issues harden late in the program.
Drive efficient failure analysis and root‑cause debug across specification, RTL, verification infrastructure, assertions, and stimulus.
Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have: Direct experience verifying CPU-subsystem power‑management features such as DVFS, power gating, retention, warm reset, and clock‑gating behavior.
Nice to have: Experience with PMC‑or power‑controller‑centric verification
Nice to have: Experience with formal verification, power‑aware simulation, emulation
Nice to have: Experience with subsystem integration issues involving resets, clock‑domain interactions