- San Jose, California, United States
- Full-time
- $149K–$238K per year
- 3+ years
Design, implement, and verify high-performance RTL for FPGA and programmable hardware solutions supporting Physical AI applications.
Compensation
$149.1K - $238.2K USD
Responsibilities
- Design and develop RTL for FPGA and programmable hardware solutions supporting Physical AI applications.
- Translate architectural specifications into high-quality, synthesizable Verilog/SystemVerilog RTL.
- Create microarchitecture specifications and participate in architecture reviews.
- Optimize designs for performance, area, power, and scalability.
- Collaborate closely with design verification teams to define verification strategies and close functional coverage.
Requirements
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
- Nice to have: Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline
- Nice to have: AI acceleration
- Nice to have: machine learning
- Nice to have: vision-processing