- Noida, Uttar Pradesh, India
- Full-time · Senior
- 5+ years
Senior Engineer responsible for FPGA/ASIC design, development, simulation, testing, debugging, verification and validation for embedded data acquisition applications.
Responsibilities
- Familiar with FPGA/ASIC design cycle Design, Development, Simulation, Test & Debug, Verification & Validation for Embedded Data acquisitions applications
- Perform FPGA/ASIC coding Development in languages like Verilog, VHDL, System Verilog
Requirements
- Bachelor's degree
- Advanced degree