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1–2 jobs· newest first

Postdoctoral Research Associate in Smart and Green AI
Northeastern University London · London, United Kingdom
£44K–£46KOn-site · Full-time · AssociateVisa
Silicon Architect, Subsystem Architecture
Meta · Sunnyvale, US+2 more
On-site

+10K new in the last hour

Postdoctoral Research Associate in Smart and Green AI

Northeastern University London · Posted Nov 9, 2026

London, England, United Kingdom
On-site
Full-time · Associate
£44K–£46K per year

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Lead design, implementation and validation of neuromorphic and in‑memory hardware accelerator prototypes for energy‑efficient AI models.

Compensation

Grade 7, 34 (£43,555 - £46,195 per annum), dependent on experience.

Responsibilities

Contribute to design, implementation and evaluation of neuromorphic and in‑memory hardware accelerator prototype boards
Develop algorithms, architectures and hardware–software co‑design methodologies for energy‑efficient AI computation
Collaborate with cross‑disciplinary teams to enable end‑to‑end system integration and validation
Publish high‑quality research outcomes in leading journals and conferences
Support supervision and mentoring of PhD and MSc students

Requirements

PhD in Computer Science, Electronics or Computer Engineering or related quantitative field

Skills

neuromorphic hardware design in‑memory computing FPGA-based test boards hardware–software co‑design memristive devices STT‑RAM emerging memory technologies machine learning models probabilistic models Transformer models state‑space models FPGA

Benefits

flexible working
parental leave opportunities
employee assistance programme
private medical insurance
season ticket loans

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Silicon Architect, Subsystem Architecture

Meta · Posted Nov 2, 2026

Sunnyvale, California, United States +2 more
On-site
2+ years

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Memory Architect on the Subsystem Architecture team responsible for on-chip memory design for wearable chips.

Locations (3)

Sunnyvale, California, United States
Redmond, Washington, United States
Austin, Texas, United States

Responsibilities

Analyze memory requirements per workload across accelerator subsystems
Evaluate SRAM options and recommend best fit
Build memory models and power, performance and area comparisons
Support studies on memory hierarchy trade-offs
Own end-to-end analysis and next-generation memory system architecture

Requirements

Bachelor's degree in Computer Science, Computer Engineering, or related technical field

Skills

memory architecture memory hierarchy analysis cache analysis SRAM circuit design SPICE memory compilers low-voltage SRAM emerging memory technologies

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