- San Jose, California, United States
- Full-time
- $106K–$154K per year
- 3+ years
Compensation
$106,200 - $153,675 USD
Responsibilities
- Develop and implement DFT strategies for FPGAs, including scan insertion, BIST (Built-In Self-Test), and test compression techniques.
- Collaborate with RTL design and verification teams to ensure testability features are embedded efficiently.
- Define and implement test plans, patterns, and fault models to ensure optimal test coverage and yield.
- Develop and maintain MBIST manufacturing test content flows and scripts.
- Perform pre-silicon test pattern simulation and validation to ensure test effectiveness prior to tape-out.
Requirements
- Bachelor's or Master's Degree in Electrical Engineering or related field
- Nice to have: Master's Degree in Electrical Engineering, or equivalent (or other related Engineering degree)
- Nice to have: Experience with Tessent MBIST flows for pattern development and knowledge of memory repair schemes and Memory algorithms
- Nice to have: Post-silicon experience including pattern conversion, Automated Test Equipment (ATE) pattern bring-up and silicon characterization