Define resilience across multi-die computing systems, translating reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, and telemetry.
Responsibilities
Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping
Define fault detection, correction, logging, and diagnosis across compute engines and cores, caches, HBM and LPDDR memory, die-to-die and scale-up links, PCIe/CXL, and management agents
Specify ECC, parity, residue checks, memory scrubbing, retirement or repair, and in-field screening to prevent and detect silent data corruption
Define end-to-end poison propagation, containment, retry, and recovery for correctable and uncorrectable errors
Specify isolation, fencing, and degraded-operation behavior for compute units, cores or clusters, memory resources, links, and package-level failures
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Nice to have: Processor error-reporting architectures
Lead the development and operation of firmware and test automation for Lightmatter’s next‑generation high‑speed optical interconnect products, owning the firmware layer, test executive, and continuous regression on bench hardware.
Compensation
$167,000—$227,000 USD
Responsibilities
Own firmware bring‑up and integration on SLT boards: boot and image management, device initialization, diagnostic APIs, register‑level read/write, mode and state control.
Validate firmware releases and drive gaps to closure with firmware team.
Own board‑level functional test integration for assembled photonic boards: firmware load, calibration, pass/fail limits, retest policy, dry‑run controls.
Architect and build the SLT test executive: configuration‑driven test sequences, instrument and device abstraction, safe‑state on abort, datalog with unit identity, test conditions, and results.
Build and operate continuous regression on bench hardware: scheduled runs, firmware and test‑content change detection, version control of test sequences and limits.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Nice to have: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Nice to have: Serial‑link or network‑port validation
Lead and govern software functional safety across the complete development lifecycle, ensuring ISO 26262 compliance and related safety principles for Stellantis software platforms.
Responsibilities
Lead and govern software functional safety across the complete development lifecycle, ensuring ISO 26262 compliance, appropriate tailoring, ASIL-dependent rigor, and consistent application of safety principles across software platforms and products.
Own the software safety strategy and technical direction, defining safety plans, responsibilities, milestones, required work products, verification and confirmation measures, acceptance criteria, and evidence required for safety approval.
Drive the definition and integrity of software safety requirements and architecture, ensuring correct decomposition, allocation, traceability, safety mechanisms, fault reactions, degraded modes, partitioning, freedom from interference, and interface assumptions.
Provide technical authority for software safety analyses and engineering decisions, including FMEA, FTA, dependent failure analysis, ASIL decomposition, diagnostic coverage, reuse justification, third-party software assessment, and tool qualification strategies.
Define and oversee ASIL-appropriate verification and validation strategies, covering reviews, static analysis, coding compliance, unit and integration testing, robustness, fault injection, structural coverage, and independence requirements throughout software development.
The role involves researching and developing countermeasures for emerging threats to embedded systems, performing security assessments, and building hardware/software prototypes to support national significance projects.
Compensation
Salary compensation range and midpoint: $126,800 - $158,500 - $190,200 Annual
Responsibilities
Research and develop new approaches and countermeasures for emerging threats to embedded systems
Design and build prototypes (hardware and software) to demonstrate advanced capabilities
Perform hands-on security assessments of embedded systems
Develop software for interfacing with and controlling lab equipment for data collection, measurement, and analysis
Shape creative and innovative ideas through internal research programs to advance the state of the art in embedded security
Deliver state of the art functional safety Platform and IP solutions to Automotive and Industrial products compliant with ISO 26262 and IEC 61508.
Responsibilities
Deliver state of the art functional safety Platform and IP solutions to Automotive and Industrial products compliant with ISO 26262 and IEC 61508.
Define safety requirements for Platform and IP modules.
Support the management of Platform and IP modules developed as SEooC through its entire lifecycle, working in close collaboration with internal Design Teams.
Prepare the safety modules for functional safety assessment.
Support SoC integration of safety Platform and IP including implementation of IP assumptions of use.
Senior Hardware Architect focused on Reliability, Availability, and Serviceability (RAS) for Tegra System-on-Chips.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 184,000 USD – 287,500 USD for Level 4; and 224,000 USD – 356,500 USD for Level 5.
Responsibilities
Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.
Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
Work closely with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
Understand the broader SoC architecture and identify how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
Requirements
MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
Nice to have: Factory or contract‑manufacturer test handoff
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