- Boston, Massachusetts, United States
- Senior
- 8+ years
Lead verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs.
Compensation
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Responsibilities
- Own verification planning and execution for a scalable cache-coherent interconnect subsystem
- Define verification strategy, test plans, environments, and closure criteria
- Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models
- Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths
- Create high-value directed and constrained-random scenarios
Requirements
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Nice to have: formal verification
- Nice to have: performance-oriented verification
- Nice to have: emulation / FPGA-assisted debug
- Nice to have: technical leadership