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1–2 jobs· newest first

Staff Software Development Engineer
Lattice Semiconductor · Penang, Malaysia
On-site · Full-time · Staff
Software Development Engineer
Lattice Semiconductor · Malaysia
Senior

+10K new in the last hour

Staff Software Development Engineer

Lattice Semiconductor · Posted Nov 6, 2026

Penang, Malaysia
On-site
Full-time · Staff
8+ years

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A successful candidate will join a team designing and developing Lattice FPGA software tools at Penang. The candidate will contribute to research, design and development of FPGA Foundation IP and IP Catalog tooling.

Responsibilities

Design and implement Digital Signal Processor (DSP) DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units targeted for integration into FPGA fabric
Develop RTL (VHDL/Verilog/SystemVerilog) for DSP hard macros and programmable DSP slices
Perform functional simulation and timing analysis to ensure correctness and performance targets are met
Engage with software and tools teams to ensure DSP IP is correctly modeled in simulation libraries and synthesis flows
Maintain existing software product tools and develop improvement plan to increase the test coverage to achieve high product quality

Requirements

Bachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline
Nice to have: functional verification methodologies
Nice to have: SystemVerilog Assertions
Nice to have: formal verification
Nice to have: synthesis and static timing analysis tools

Skills

RTL design Verilog VHDL SystemVerilog DSP theory and algorithms filtering FFT fixed-point arithmetic sample-rate conversion Synopsys Design Compiler PrimeTime Radiant Quartus

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Software Development Engineer

Lattice Semiconductor · Posted Nov 6, 2026

Penang, Malaysia
Senior
6+ years

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Design and develop FPGA software tools and IP at Lattice in Penang.

Responsibilities

Design and implement DSP foundation IP blocks
Develop RTL for DSP hard macros and programmable DSP slices
Perform functional simulation and timing analysis
Engage with software and tools teams to model DSP IP in simulation libraries and synthesis flows

Requirements

Bachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline

Skills

RTL design using Verilog, VHDL, or SystemVerilog DSP theory and algorithms: filtering, FFT, fixed-point arithmetic, sample-rate conversion Functional verification methodologies (SystemVerilog Assertions, formal verification)Synthesis and static timing analysis tools (Synopsys Design Compiler, PrimeTime, Radiant, Quartus)

FPGA architectures and programmable DSP slice design

Synopsys Design Compiler

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