Referso Jobs

Young Graduate Trainee

Infineon · Posted Nov 4, 2026

Open

Bangalore, India
Entry
1–3 years

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Young Graduate Trainee

Infineon · Posted Nov 4, 2026

Open

Bangalore, India
Entry
1–3 years

Apply with Referso

VLSI Physical Design / APR Engineer

Ambarella · Posted Aug 24, 2026

Open

Hsinchu, Taiwan, Taiwan
2–7 years

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Responsible for implementing and optimizing the layout of integrated circuits from netlist to GDSII, ensuring electrical performance, area, and power goals are met and physical verification results are good.

Responsibilities

Derive full-chip and block-level physical design from netlist to tape-out
Floorplanning, power planning, placement, clock tree synthesis, routing, and layout verifications
Work closely with front-end design, DFT, and package teams to ensure design closure
Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis, IR drop analysis, EM analysis, and physical verification
Analyze, optimize and resolve congestion, timing, power integrity and signal integrity issues

Requirements

Master degree majoring in EE/CE/CS related fields
Nice to have: 10/7/5/3nm design experience
Nice to have: manager positions
Nice to have: communication
Nice to have: team spirit

Skills

VLSI Cadence Synopsys Mentor floorplanning

Lead DFT Engineer (Scan Insertion | ATPG | MBIST )

Advanced Micro Devices, Inc · Posted Nov 4, 2026

Open

Bangalore, Karnataka, India
Senior
12+ years

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Lead DFT Engineer responsible for design, implementation, and verification of DFT architecture and features for AMD’s front‑end design/integration team.

Responsibilities

Implement and verify DFT architecture and features
Insert scan and generate ATPG patterns
Verify ATPG patterns with gate‑level simulation
Analyze test coverage and test cost reduction
Provide post‑silicon support to enhance yield learning

Requirements

Bachelor's or Masters degree in Computer Engineering or Electrical Engineering
Nice to have: IEEE1500
Nice to have: JTAG 1149.x
Nice to have: Scan methodology
Nice to have: Memory BIST

Skills

Design for Test (DFT) architecture Scan insertion ATPG pattern generation Gate‑level simulation Test coverage analysis Post‑silicon support Mentor testkompress

Perl scripting jobs

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