Entry-level analog layout engineer responsible for translating circuit designs into manufacturable physical layouts and performing layout verification.
Responsibilities
Develop physical layouts for analog and mixed-signal integrated circuits
Translate schematic designs into physical layouts
Perform layout verification including DRC and LVS
Collaborate with analog designers and other engineering teams
Apply layout best practices to optimize area, matching, symmetry, parasitics, and signal integrity
Requirements
Bachelor’s degree in Electrical Engineering, Electronics Engineering, Mechatronics Engineering, or a related engineering discipline
Nice to have: exposure to CMOS technology
Nice to have: semiconductor devices
Nice to have: microelectronics
Nice to have: background in basic analog circuit concepts
Lead physical design verification for Microsoft’s cloud infrastructure chips.
Compensation
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Work closely with Physical Design Engineers on LVS, DRC, ERC, Antenna fixes
Drive full chip integration for physical design verification, signoff and Tape‑outs
Collaborate with clock, analog, integration teams on routing, power delivery, block integration
Work with 3pIP and 1pIP teams for SOC‑IP handshake
Work with CAD team, tool vendors, foundry and partners to develop and validate new tools, flows, runsets
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: BS/MS in Electrical or Computer Engineering
Nice to have: 5+ years of experience in semiconductor chip design/SOC physical design
Lead complex customer engagements using ICV and StarRC, diagnose and resolve advanced physical verification and parasitic extraction issues, develop methodologies, and provide technical guidance to engineers.
Responsibilities
Own complex customer engagements using ICV and StarRC
Debug advanced physical verification and parasitic extraction issues
Determine methods and procedures for new assignments
Develop and refine ICV and StarRC methodologies
Support integrated flows and advanced ICV and StarRC verification and extraction capabilities
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline
Lead ECAD responsibilities for high‑speed PCB design and manufacturing support
Responsibilities
10+ years of experience in PCB Design & Design Practices
Experience in High Speed PCB Design [DDR 4, LPDDR, PCIe, MIPI 10 Gig+ etc]
Hands on Experience in Power Rails, Analog PCB design, Clock and appropriate component placements to meet the design compliance
Experience in Library Part Creation, Placement, Routing, DRC setting up and DRC error clearance, Generation of Hype File for SI and PI analysis, Generation of Step Files /.dxf files , Gerber and Manufacturing file generation, Penalisation, Manufacturing file verification through CAM and DFM verification with Valor Tool
Understand the component data sheet and Create the Library parts
Silvaco is hiring a Memory Design Lead to drive the architecture, design, customer interface and delivery of our embedded memory compiler portfolio: single-port SRAM, ROM, single- and dual-port register files (1PRF, 2PRF), and dual-port RAM (DPRAM).
Responsibilities
Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM.
Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy and repair strategy, and assist circuits (read/write assist, body bias) to hit aggressive PPA targets.
Drive Vmin, leakage, performance, area, and yield optimization across PVT corners, process variation, and aging effects.
Own the technical roadmap for the memory portfolio: new compiler variants, new nodes, feature enhancements, and methodology improvements.
Establish design, verification, and signoff methodology, while leading design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification.
The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting edge foundry technology.
Responsibilities
Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
Floorplan, route, and assemble lower-level cells into macros
Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.
Requirements
Electrical Engineering Degree
Mechanical Engineering Degree
Electronics related Diploma
Nice to have: CMOS device/circuit theory
Nice to have: analog/digital layout best practices
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