- Fort Collins, Colorado, United States
- Senior
- $110K–$176K per year
- 6+ years
Design, implement, and maintain advanced verification infrastructure for ASIC products.
Compensation
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
Responsibilities
- Architect and develop robust, scalable, and reusable verification environments using SystemVerilog and UVM
- Author detailed verification plans and develop, execute, and debug directed and constrained-random test cases
- Track, analyze, and maximize functional and code coverage metrics
- Write SystemVerilog Assertions (SVA) to implement assertion-based verification
- Establish, maintain, and optimize operation processes for design database management and official database releases
Requirements
- Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
- Master’s Degree in a related field