Sr. Staff Physical Design Engineer
Advanced Micro Devices, Inc · Austin, US+1 more Senior
CPU Implementation Engineer
Apple · Cupertino, US+1 more · On-site · Full-time
Physical Design Lead, ASIC
Google · Sunnyvale, US· On-site
+10K new in the last hour
Advanced Micro Devices, Inc · Posted Nov 9, 2026
Lead complex physical design work for multi‑million‑gate graphics IP blocks in AMD’s next‑generation AI data center chips.
Austin, Texas, United States Santa Clara, California, United States Own the physical design of complex, multi‑million‑gate graphics IP blocks and drive designs toward required performance, power, and area targets. Partner with RTL design teams to identify frequency bottlenecks and address logic‑level and timing issues early in the project lifecycle. Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification. Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff. Establish and improve physical design methodologies for large IP delivery, including IP integration and design‑quality checks. Bachelor's in Electronics/Electrical Engineering Master's in Electronics/Electrical Engineering Nice to have: AI techniques for performance, power, and area optimization Apple · Posted Nov 5, 2026
Work on block and full-chip EM/IR and electrical verification, power grid construction, and implementation tasks for Apple’s chip designs.
Cupertino, California, United States United States base pay range for this role is between $174,149 - $225,300/yr
Work on block and full-chip EM/IR and electrical verification Work on power grid and methodologies and implementation Script using Perl/Python to automate tasks and improve debug efficiency Work with implementation/CAD team during full design cycle to drive analysis fixes/signoff closure for takeout Analysis and comparison of various tool methodologies to determine the best suited for Power grid construction Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field Google · Posted Nov 4, 2026
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff. Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure. Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools - Synopsys Fusion Compiler, Cadence Innovus/Genus, PrimeTime, StarRC, Calibre, Apache Redhawk. Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture Comprehensive medical and dental coverage retirement benefits discounted products and free services tuition reimbursement discretionary restricted stock unit awards
Nice to have: structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks)
Sr. Staff Physical Design EngineerNewAdvanced Micro Devices, Inc · Austin, US+1 more
CPU Implementation EngineerApple · Cupertino, US+1 more
Physical Design Lead, ASICGoogle · Sunnyvale, US