Lead RTL Design Engineer for Mixed‑Signal IPs, responsible for developing, integrating, and verifying digital RTL blocks within mixed‑signal subsystems.
Responsibilities
Develop synthesizable, high‑quality RTL for mixed‑signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front‑ends.
Collaborate with analog design engineers to define digital‑analog interface specifications, control logic, and communication protocols.
Ensure correct functionality and performance of mixed‑signal IPs through behavioral modeling, simulation, and co‑verification with analog components.
Participate in design reviews, micro‑architecture definition, and documentation of IP functionality and timing interfaces.
Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.
Requirements
B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering
Lead Software Engineer – Power Optimization focused on designing and developing advanced optimization algorithms and scalable software solutions for complex power optimization challenges in digital designs.
Responsibilities
Design and develop advanced algorithms for power optimization, including clock gating, data gating, glitch power optimization, and related methodologies.
Develop scalable, high-performance software solutions for PowerPro optimization and analysis flows.
Analyze complex digital designs and power behavior to identify optimization opportunities.
Drive technical design, implementation, testing, and delivery of software features.
Collaborate with cross-functional teams to deliver innovative power optimization solutions.
In this role, you’ll work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology and developing custom silicon solutions for Google.
Own the planning, creation and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume.
Resolve structural or physical issues related to the integration of complex ASICs and SOCs and collaborate with teams across Google to develop ideas for high impact Silicon and hardware projects.
Manage all cross-functional interactions related to top-level floorplanning of chip projects.
Develop and improve floorplan implementation methodologies.
Support and execute implementation flows using both industry-standard and specialized internal tools.
Requirements
Bachelor's degree in Electrical Engineering
Computer Engineering
Computer Science
a related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science
Lead development of CAD software and DevOps workflows for silicon design teams.
Compensation
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
Responsibilities
Be a developer in a central CAD Software team that owns a common tool stack to internal SoC and IP designs.
Create and maintain CAD DevOps workflows, including CI/CD, cloud-based EDA environments, and automation frameworks.
Follow software practices within the CAD Software team.
Work in close collaboration with the CAD Hardware and Compute infrastructure teams.
Design software solutions and documentation that scale to a large user base.
Requirements
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: 4+ years of experience in Software development
Nice to have: 6+ years of relevant experience
Nice to have: Experience owning and driving end to end software development life cycle for multiple complex software projects
The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
Lead technical strategy and execution for CAD DevOps workflows
Lead team to follow industry-standard software practices
Work in close collaboration with the CAD Hardware and Compute infrastructure teams
Design software solutions and documentation that scale to a large user base
Develop, enhance, and integrate CAD Flows and automation for organization-wide use
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
As an Electronic Design Automation (EDA) Software Engineer within Altera you will be working on one of the most fascinating technology used in big data centers - The Field Programmable Gate Arrays (FPGA).
Compensation
Estimated Salary Range: $110K – $120K CAD
Responsibilities
Developing high quality C/C++ software code for enabling placement and mapping of peripheral components in FPGAs.
Owning, developing and enhancing tools that automate the Device Modeling of peripheral components of FPGA.
Owning the hardware/software co-design architecture of various blocks.
Designing and implementing new features based on the hardware/software co-design architecture as well enhancing existing features while maneuvering your way through a huge code base.
Owning various analytical/logical/CAD tasks involved in device modeling and compilation of various peripheral components.
Circuit Design Engineer responsible for defining, specifying, and implementing advanced PLL IPs for AMD products.
Responsibilities
Design complex PLL building blocks including architecture development and transistor level circuit design
Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements
Work closely with mask design engineers to deliver the physical design and define production/bench-level test plans with post-silicon characterization groups
Physical Design EngineerNewAdvanced Micro Devices, Inc · Shanghai, China
SoC Silicon Top-Level Floorplan EngineerNewGoogle · Sunnyvale, US