- Bengaluru, Karnataka, India
- 5–7 years
Responsibilities
- Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation
- Block level implementation from netlist to GDS
- Handling timing closure of high frequency blocks
- Handling blocks of high instance counts – 1M instance and above
- Expertise in signoff closure – Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level