Bit Error Rate Testers (BERT) jobs

Optical Transport Senior Network Implementation Engineer

Google · Posted Nov 12, 2026

Open

Thornton, Colorado, United States +1 more
On-site
Senior
$150K–$217K per year

Optical Transport Senior Network Implementation Engineer

Google · Posted Nov 12, 2026

Open

Thornton, Colorado, United States +1 more
On-site
Senior
$150K–$217K per year

Senior Test & Evaluation Lab Electromagnetic Compatibility Technician

Boeing · Posted Nov 11, 2026

Open

Seattle, Washington, United States
Senior
$81K–$109K per year

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Senior Test & Evaluation Lab Electromagnetic Compatibility Technician

Compensation

Summary Pay Range: $80,750 - $109, 250

Responsibilities

Set up and operate RF and EMC test equipment, including spectrum analyzers, signal generators, power amplifiers, and EMI receivers
Conduct radiated and conducted emissions/immunity tests in accordance with standards such as DO-160 and MIL-STD-461
Configure test environments in shielded rooms
Assist in troubleshooting RF interference issues and documenting root causes
Maintain calibration records and ensure all test equipment meets requirements

Requirements

Nice to have: EMC or RF testing environment
Nice to have: Familiarity with EMC standards
Nice to have: Troubleshooting RF signal paths
Nice to have: Grounding and shielding

Skills

RF test instrumentation Spectrum analyzers Network analyzers Power meters Bit error rate testers

SerDes Applications Engineer

Broadcom · Posted Nov 11, 2026

Open

San Jose, California, United States
On-site
Full-time · Senior
$144K–$230K per year
10+ years

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SerDes Applications engineer for ASIC Product Division (APD). Work as part of a team of highly skilled applications engineers providing first class support to customers from pre-sales to product deployment.

Compensation

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

Responsibilities

Validation of SerDes performance on test silicon with setup and external channel(s) representing customer application
Working with SI and SerDes development team to resolve any performance marginality observed
Testing evaluation boards with test silicon, documentation of the hardware and software for deployment at customer site
Development of software/scripts to enable customers to be able to run large number of loops with voltage, temperature margining over different configurations and channels
Support customer queries related to configuration of the SerDes, initialization sequence, API, reference clock requirement, power noise specifications

Requirements

MSEE
Nice to have: signal integrity
Nice to have: cross talk
Nice to have: power noise

Skills

high speed serial interfaces design equalization techniques

Senior Test & Evaluation Lab Electromagnetic Compatibility Technician

Boeing · Posted Nov 11, 2026

Open

Seattle, Washington, United States
On-site
Full-time · Senior
$81K–$109K per year

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Senior Test & Evaluation Lab Electromagnetic Compatibility Technician

Compensation

Summary Pay Range: $80,750 - $109, 250

Responsibilities

Set up and operate RF and EMC test equipment, including spectrum analyzers, signal generators, power amplifiers, and EMI receivers
Conduct radiated and conducted emissions/immunity tests in accordance with standards such as DO-160 and MIL-STD-461
Configure test environments in shielded rooms
Assist in troubleshooting RF interference issues and documenting root causes
Maintain calibration records and ensure all test equipment meets requirements

Requirements

Nice to have: EMC testing environment
Nice to have: EMC standards familiarity
Nice to have: attention to detail
Nice to have: methodical approach
Nice to have: written communication

Skills

RF test instrumentation spectrum analyzers network analyzers power meters

Staff SerDes Characterization Engineer, Platforms

Google · Posted Nov 11, 2026

Open

Sunnyvale, California, United States
On-site
Full-time · Staff
$188K–$274K per year
6+ years

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Own transmitter and receiver characterization and compliance testing for SerDes interfaces across next-generation compute and networking platforms.

Compensation

US: $188000 - $274000 (USD) + 20% bonus target + equity + benefits

Responsibilities

Own transmitter and receiver characterization and compliance testing for SerDes interfaces across next-generation compute and networking platforms.
Lead the development of advanced RX test methodologies, including jitter tolerance, stressed receiver sensitivity, bit error rate, and complex inter symbol interference channel testing.
Interpret and map industry standards (IEEE 802.3, OIF-CEI) into rigorous, automated receiver test plans.
Master and deploy high-bandwidth lab instrumentation, including high-speed arbitrary waveform generators, bit error rate testers, real-time oscilloscopes, and vector network analyzers.
Collaborate closely with ASIC PHY design, silicon design and validation, and signal integrity teams to root-cause link performance anomalies and optimize TX and RX equalizer and DSP parameters.

Requirements

Bachelor's degree in Electrical Engineering
Bachelor's degree in Computer Engineering
Bachelor's degree in Physics
Bachelor's degree in a related field
PhD degree in Electrical Engineering

Skills

Senior Validation Engineer

Microsoft · Posted Nov 9, 2026

Open

Mountain View, California, United States
On-site
Full-time · Senior
$120K–$261K per year
5+ years

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Senior Validation Engineer with expertise in functional, electrical, high speed interfaces, memory, power/performance, debug/BU and tool development within the Post-Silicon Validation team.

Compensation

The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Responsibilities

Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements
Write test plans and implement them by developing test content, scripts, tools, and other verification collateral
Execute content in post-silicon, triage, and debug failures
Engage with partners to drive continuous improvement to design, validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise

Requirements

Doctorate in Electrical Engineering
Doctorate in Computer Engineering
Doctorate in Computer Science
Master's Degree in Electrical Engineering
Master's Degree in Computer Engineering

Skills

Functional validation

Electrical Validation Engineer

Intel Corporation · Posted Nov 6, 2026

Open

Guadalajara, Mexico
Hybrid
Contract
1+ years

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Electrical Validation Engineer

Responsibilities

Execute and track electrical validation test plan strategies of the Analog Front End (AFE) and end-to-end interconnections across Intel Xeon D platforms.
Perform test setups and configurations across interfaces such as Networking (Eth, CPRI) and Mem (DDR5, LPDDR5x).
Validate conformance to networking and JEDEC industry standards and Intel specifications.
Apply Intel developed validation disciplines, including Signal Integrity (SI) Validation, System Marginality Validation and/or Interoperability methodologies and processes.
Develop debug documentation with lab experiences during execution and system issues resolution.

Requirements

Bachelor's degree in electrical engineering, Computer Engineering, or a related field.
Nice to have: Master's degree in electrical engineering, Computer Engineering, or a related field.
Nice to have: proficiency in Memory technologies (RDIMM, UDIMM, SODIMM, MRDIMM)
Nice to have: networking protocols (Ethernet, CPRI technologies)
Nice to have: familiarity with debugging tools and validation methodologies

Skills

hardware validation signal integrity

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