Circuit Design Engineer responsible for defining, specifying, and implementing advanced PLL IPs for AMD products.
Responsibilities
Design complex PLL building blocks including architecture development and transistor level circuit design
Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements
Work closely with mask design engineers to deliver the physical design and define production/bench-level test plans with post-silicon characterization groups
Design and develop advanced components of the memory sub-system and related logic for Microsoft’s cloud hardware infrastructure.
Compensation
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
Responsibilities
Be part of a design team developing advanced components of the memory sub-system
Develop automation and AI based solutions to improve organizational efficiency
Own design blocks within complex, coherent fabrics, and bridge IPs
Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc
Collaborate with team members to define interfaces and make optimal design choices
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
Integration Design Engineer focused on Custom and Digital Design Implementation, specializing in Verilog and System Verilog for programmable logic solutions.
Responsibilities
Custom Design Flow management
Semiconductor principles and transistor-level analysis
Schematic and layout Entry using Cadence Virtuoso
Characterization, performance, and power simulations
The Engineer will be responsible for working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM, executing block-level place and route assignments from Netlist through GDS flow.
The Senior Engineer - ASIC PD is responsible for floor-planning, timing constraints, physical synthesis, and executing physical design through GDS flow.
Senior Systems Software Developer responsible for maintaining and augmenting the WiFi and Networks subsystem on both native and virtualized systems, providing technology leadership in architecture, design, and performance.
Compensation
attractive compensation & bonus package
Responsibilities
Develop and maintain Wi-Fi and Networking driver components in an open-development environment.
Create and document software specifications and designs that address the needs of QNX customers.
Provide project estimates for requirement, design, implementation, and test efforts.
Provide clear communication with development team members, technical leads, and management on project status, risks and approaches.
Conduct design reviews, code reviews and unit test with technical peers.
PLL Design EngineerNewAdvanced Micro Devices, Inc · San Diego, US
Lead HandlerConstellis · Miami, US