- Jerusalem, Jerusalem District, Israel
- On-site
- Full-time · Mid
- 3+ years
Own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
Responsibilities
- Block level PnR, floor-planning, clock, power planning and distribution
- Static Timing closure using commercial tools
- Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )
Requirements
- B.Sc / M.Sc Electric Engineering
- B.Sc / M.Sc Computer Engineering
- Nice to have: Verilog
