- San Jose, California, United States +2 more
- Senior
Define next-generation SoCs for automotive, robotics, vision, and Physical AI applications, translating real-world workloads into quantitative SoC requirements spanning compute, memory, bandwidth, interconnect, data movement, power, and end-to-end latency.
Locations (3)
- San Jose, California, United States
- San Diego, California, United States
- Austin, Texas, United States
Responsibilities
- Translate Physical AI, automotive, robotics, and vision workloads into SoC compute, memory, bandwidth, interconnect, and latency requirements.
- Model end-to-end data flows across sensor, CPU, AI accelerators, memory hierarchy, on-chip interconnect, and I/O.
- Analyze and optimize data placement and movement across DDR memory, caches, on-chip memory, accelerator-local memory, and buffers.
- Correlate AI compute requirements and accelerator performance with memory bandwidth, data movement, utilization, and system-level performance.