- Munich, Bavaria, Germany
- On-site
- Full-time · Senior
Take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals.
Responsibilities
- Own block level PnR, floor-planning, clock and power distribution
- Get involved with static timing closure with commercial tools
- Do power & noise analysis (EM/IR-Drop/Xtalk) as well as layout verification (DRC/LVS)
- Develop and validate dedication low power clock network guidelines
- Resolve design and flow issues related to physical design and identify potential solutions
Requirements
- MSEE or equivalent strong experience
- Nice to have: Verilog
- Nice to have: Hierarchical design approach
- Nice to have: Top-down design
- Nice to have: RC extraction and correlation