Physical Design Engineer
Apolis · Posted Nov 6, 2026
- Austin, Texas, United States
- On-site
- Full-time · Mid
- 5+ years
Responsible for digital implementation from synthesized netlist through final GDSII release, including floorplanning, power planning, place-and-route, clock-tree synthesis, timing closure, physical verification, power integrity analysis, and tapeout signoff.
Responsibilities
- Drive block-level and full-chip physical design implementation from netlist to GDSII
- Develop and execute floorplanning, power planning, placement, clock-tree synthesis (CTS), routing, and physical optimization flows
- Own timing closure across multiple operating modes including functional, scan shift, and scan capture modes
- Develop, optimize, and maintain CTS methodologies and scripts to support complex clock architectures and scan requirements
- Perform static timing analysis (STA) and resolve setup, hold, clock skew, insertion delay, transition, and timing constraint violations
Requirements
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field