Silvaco is hiring a Memory Design Lead to drive the architecture, design, customer interface and delivery of our embedded memory compiler portfolio: single-port SRAM, ROM, single- and dual-port register files (1PRF, 2PRF), and dual-port RAM (DPRAM).
Responsibilities
Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM.
Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy and repair strategy, and assist circuits (read/write assist, body bias) to hit aggressive PPA targets.
Drive Vmin, leakage, performance, area, and yield optimization across PVT corners, process variation, and aging effects.
Own the technical roadmap for the memory portfolio: new compiler variants, new nodes, feature enhancements, and methodology improvements.
Establish design, verification, and signoff methodology, while leading design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification.
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing. Lead definition, design, verification, and/or documentation for ASIC development.
Responsibilities
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing
Lead definition, design, verification, and/or documentation for ASIC development
Determine architecture design, logic design, and/or system simulation
Define module interfaces/formats for simulation
Lead the development of multidimensional designs involving the layout of complex integrated circuits
Develop chip package board PDN models and perform simulations to verify supply noise, impedance, and transient response; define PI requirements, specifications, and decoupling strategies; debug and root cause PI issues; correlate silicon measurements with simulations; collaborate with architecture, silicon, package, and board teams to deliver system aware PI solutions; improve PI methodologies, automation flows, and analysis processes.
Responsibilities
Develop chip package board PDN models and perform simulations to verify supply noise, impedance, and transient response
Define PI requirements, specifications, and decoupling strategies for all major power rails
Debug and root cause PI issues during bring up, validation, and production phases
Correlate silicon measurements with simulations and refine models accordingly
Collaborate with architecture, silicon, package, and board teams to deliver system aware PI solutions
Requirements
Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
The PDK team works with internal and external foundries to develop and deploy high-quality PDKs on both mature and advanced nodes. The role involves enhancing support for business units and taking over critical activities.
Responsibilities
Install/customize foundry PDKs and provide support for various product groups.
Develop, review, update and release foundry PDK and design methodologies for various business units.
Support circuit design and layout team with PDK related tasks such as design migrations, simulation, physical verification (DRC/LVS/ERC), EMIR, and parasitic extraction (PEX/QRC/StarRC).
Provide CAD support to designers in troubleshooting project setup, design environment configuration, tool integration, and day-to-day environment issues to ensure a stable and productive design flow.
Own technically complex PDK/CAD problems from investigation through resolution.
The Engineer will lead Broadcom's design methodology for 5nm and lower technology silicon, focusing on floor-planning, placement, CTS, route, and physical verification.
Responsibilities
Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
Maintain deep functional knowledge of P&R flows
Implement timing and functional ECO
P&R, Extraction, Physical verification, work towards STA closure
Build automation flows wherever needed/adapt to existing flows for re-use
Physical Design Engineer works with the logic design team to drive physical aspects, complete netlist to GDS2 implementation, and manage timing timing, physical, and electrical verification for SoC partitions.
Locations (2)
Cupertino, California, United States
United States
Compensation
The base pay range for this role is between $174,149 - $225,300/yr
Responsibilities
Work with logic design team to understand partition architecture and drive physical aspects early in design cycle
Complete netlist to GDS2 implementation for partition(s) meet schedule and design goals
Be responsible for timing, physical & electrical verification, driving the signoff closure for the partitions
Resolve design and flow issues related to physical design, identifying potential solutions and driving execution
Be a focal point for place and route, driving the work among place and route engineers, setting goals and milestones, planning short and long-term work
SMTS Silicon Design EngineerAdvanced Micro Devices, Inc · San Diego, US
Physical Design EngineerApple · Cupertino, US
Digital Signal Processing (DSP) EngineerHII's Mission Technologies division · Dayton, US