- Sunnyvale, California, United States
- On-site
- $163K–$236K per year
Design and verify low‑power ASICs for Google’s TPU architecture, developing testbenches, simulation environments, and power‑analysis workflows.
Compensation
US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Responsibilities
- Define low power verification strategies and methodologies for complex ASIC designs.
- Author comprehensive low power verification plans targeting UPF‑defined power domains and states.
- Develop power‑aware testbenches and simulation environments using SystemVerilog and UVM.
- Verify power intent utilizing static low power verification tools like VC LP or Conformal LP.
- Run gate‑level simulations with power‑aware models to validate power‑up and power‑down sequences.
Requirements
- Nice to have: low‑power digital design
- Nice to have: advanced process nodes
- Nice to have: Verilog
- Nice to have: VHDL
- Nice to have: SystemVerilog