- Tampere, Pirkanmaa, Finland
- Entry
Junior SoC Verification Engineer responsible for RTL design, IP integration and verification of ultra‑low power chips.
Compensation
Competitive salary with bonus plan (Short term incentive + Long term incentive)
Responsibilities
- Plan SoC/IP subsystem verification
- Develop test infrastructure and functional verification
- Write embedded C and CPU‑centric tests
- Define, implement and analyze coverage
- Generate test benches and cases using Verilog, SystemVerilog & UVM
Requirements
- MSc in electrical engineering
- Bachelor with industrial experience
- Nice to have: AI tools
- Nice to have: LLM-based coding assistants